1. Field of the Invention
The present invention relates to a semiconductor device fabricating method including a wafer processing process and a wiring process and, more specifically, to contact hole forming techniques.
2. Description of the Related Art
Minimum device dimensions specified by pattern rules have progressively been decreased with the ongoing miniaturization of semiconductor devices, such as LSI circuit devices, and the growth of the number of components per IC chip. The decrease of minimum device dimensions affects the photolithographic process most significantly. The effect of the dislocation of a pattern of components of a semiconductor device, such as a pattern of transfer gates or contact holes, due to errors in pattern alignment in an exposure process relative to the size of the pattern increases with the miniaturization of the pattern, and affects the characteristics of semiconductor device. From the viewpoint of the resolution of photolithography, errors in pattern alignment cannot completely be eliminated. When forming contact holes, it is desired that the contact holes are isolated from adjacent components, such as gates, even if the positions of the contact holes are dislocated relative to the adjacent components.
A prior art semiconductor device fabricating method meeting such a demand will be described with reference to FIGS. 16 to 18. FIGS. 16(A) to 16(D) are enlarged typical sectional views illustrating a workpiece in substrate processing steps of a method of fabricating a DRAM (dynamic random-access memory), and FIGS. 17(A), 17(B), and 18(A) to 18(C) are enlarged typical sectional views illustrating the workpiece in wiring pattern forming steps of the same method. Generally, the DRAM is basically a CMOS circuit formed by connecting n-channel MOSFETs and p-channel MOSFETs by wiring lines.
Referring to FIG. 16(A), n-type regions (n-type wells) 11 and p-type regions (p-type wells) 12 are formed in a surface of a silicon wafer 10 by ion implantation, and element isolation regions 13 and 14 are formed by selective oxidation. A plurality of transfer gates 20 are formed on the silicon wafer 10. The transfer gates 20 are formed by forming a gate oxide film 21, a gate polysilicon film 22 and a silicon dioxide film 23 in that order on the surface of the silicon wafer 10. In this specification, the silicon dioxide film 23 as a component of the transfer gate 20 will be called an "offset silicon dioxide film" because the silicon dioxide film 23 displaces (offsets) the upper surface of the transfer gate 20 relative to the gate polysilicon film 22 serving as an actual conductive layer.
The gate oxide film 21, the gate polysilicon film 22 and the offset silicon dioxide film 23 are formed over the entire surface of the silicon wafer 10. A resist film is formed over the silicon dioxide film 23, the resist film is etched in a pattern corresponding to the transfer gates 20 by an ordinary photolithographic process, the offset silicon dioxide film 23 is etched by a dry etching process using the gate polysilicon film 22 as a stopper. Then, the resist film is removed by ashing, and the gate polysilicon film 22 is etched by a dry etching process using the offset silicon dioxide film 23 as a mask to form the transfer gates 20.
The offset silicon dioxide film 23 is used as a mask to avoid the chipping of a thin resist film when forming a thick transfer gates 20 by etching a thick layer by an etching process using the thin resist film. The thickness of a resist film which can be developed by exposing the same to light on an aligner is dependent on the depth of focus of the aligner. When forming a minute pattern by photolithography, an aligner having a large numerical aperture (N.A.) must be used to secure a high resolution. The depth of focus decreases when the numerical aperture increases. Thus the thickness of the resist film which can be developed decreases as the minuteness of the pattern of the resist film increases. Therefore, a mask like the offset silicon dioxide film 23 is necessary for etching a thick film to form high steps.
A region on the left side, as viewed in FIG. 16, of the element isolation region 13 is a peripheral circuit region Rp in which transistors are arranged in a relatively low density, and a region on the right side, as viewed in FIG. 16, of the element isolation region 13 is a memory cell region Rm in which transistors are arranged in a relatively high density. The p-type wells 12 in both the regions are masked with a resist film and an n-type impurity is injected into the p-type wells 12 as indicated by the arrows by an ion implantation process to form n-type diffused layers 15 which serve as source/drain regions of n-channel MOS transistors. A resist pattern for the ion implantation process is not shown.
Then, a silicon dioxide film is deposited over the entire surface of the wafer by a chemical vapor deposition (CVD) process, the silicon dioxide film is etched by an anisotropic etching process to form side walls 30 on the side surfaces of the transfer gates 20 as shown in FIG. 16(B). The side walls 30 are formed in a width necessary for the side walls 30 to serve as a mask when forming diffused layers which serve as the source/drain regions of the MOS transistors of the peripheral circuit region Rp.
Subsequently, as shown in FIG. 16(C), a mask is formed by an ordinary photolithographic process so as to cover regions other than the p-type well and the n-type well of the peripheral circuit region Rp, and the p-type well of the peripheral circuit region Rp is doped with an n-type impurity and the n-type well of the peripheral circuit region Rp is doped with a p-type impurity by an ion implanting process to form p.sup.+ -type diffused layers 16 and n.sup.+ -type diffused layers 17 as the source/drain regions of the MOS transistors of the peripheral circuit region Rp. The MOS transistors of the memory cell region Rm perform merely an ON/OFF operation so that p.sup.+ -type diffused layers and n.sup.+ -type diffused layers need not be formed in the memory cell region Rm. The MOS transistors of the peripheral circuit region Rp needs the p.sup.+ -type diffused layers 16 and the n.sup.+ -type diffused layers 17 for an amplifying operation. The side walls 30 determine the positions of regions to be subjected to the ion implantation process, i.e., determine the positional relation between the diffused layers 16 and 17, and the transfer gate 20, which determines the characteristics of the MOSFETs. The resist pattern for the ion implantation process is not shown in FIG. 16(C).
After the diffused layers 16 and 17 have been formed in the peripheral circuit region Rp, a silicon nitride film 31, which serves as a stopper when forming contact holes by an etching process, is formed over the entire surface of the wafer as shown in FIG. 16(D), a silicon dioxide film 32 (as shown in FIG. 17) is deposited over the silicon nitride film 31, and the surface of the silicon dioxide film 32 is flattened by a chemical mechanical polishing (CMP).
In a wiring process, a resist film is patterned by an ordinary photolithographic process to form a mask 40 as shown in FIG. 17(A) for forming contact holes reaching the silicon wafer 10 in the memory cell region Rm. The silicon dioxide film 32 is etched by using the mask 40 and using the silicon nitride film 31 as a stopper, and then contact holes 41 reaching the silicon wafer 10 are formed by etching the silicon nitride film 31.
The mask 40 is removed by ashing and a polysilicon film is formed so as to fill up the contact holes 41. The surface of the workpiece is etched back to form pads 50 as shown in FIG. 17(B). The pads 50 are connected to capacitor electrodes which are to be formed later.
After the pads 50 have been formed, a silicon dioxide film 33, i.e., an insulating layer, is deposited as shown in FIG. 18(A), and contact holes are formed to connect bit lines formed on the silicon dioxide film 33 to the silicon wafer 10 in the memory cell region Rm. A resist film formed on the silicon dioxide film 33 is patterned by an ordinary photolithographic process to form a mask 42, the silicon dioxide films 33 and 32 covered with the mask 42 are etched by using the silicon nitride film 31 as a stopper, and then the silicon nitride film 31 is etched to form contact holes 43 reaching the silicon wafer 10.
Since the silicon dioxide film 32 is etched by using the silicon nitride film 31 as a stopper, the contact holes 41 and 43 reaching the silicon wafer 10 can be formed without causing insulation breakdown in the transfer gates 20 even if the openings of the mask for forming the contact holes 41 and 43 are dislocated from their correct positions.
Subsequently, contact holes reaching the gate polysilicon film 22 of the transfer gates 20 formed in the peripheral circuit region Rp are formed. The mask 42 is removed by ashing, a mask 44 having openings reaching the transfer gates 20 as shown in FIG. 18(B) are formed by an ordinary photolithographic process, and the silicon dioxide films 33 and 32, the silicon nitride film 31 and the offset silicon dioxide film 23 are etched to form contact holes 45 reaching the transfer gates 20.
The mask 44 is removed by ashing, a bit line film 34 is formed, a mask 46 of a pattern corresponding to bit lines is formed by an ordinary photolithographic process, and the bit line film 34 is etched by using the mask 46 and using the silicon dioxide film as a stopper to form bit lines as shown in FIG. 18(C). After the bit lines have been formed, capacitor electrodes are formed to accomplish a wafer processing process (preparatory process) for fabricating a DRAM. Then, the workpiece is tested, and the workpiece is subjected to a packaging process (finishing process) to complete a semiconductor device.
In this conventional semiconductor device fabricating method, however, the side walls 30 necessary for forming the diffused layers 16 and 17 of the peripheral circuit region Rp are formed on the side surfaces of the transfer gates 20 of the memory cell region Rm and remain unremoved until the final process. Therefore, regions for the silicon nitride film 31 formed as a stopper between the transfer gates 20 are relatively narrow, which is an impediment to the miniaturization of the semiconductor device. If the semiconductor device of the foregoing configuration is miniaturized and the intervals between the transfer gates 20 are reduced, regions between the side walls 30 are covered with the silicon nitride film 31, which makes it difficult to form the contact holes 41 and 43 reaching the silicon wafer 10 without causing insulation breakdown in the transfer gates 20; that is, if the contact holes 41 and 43 are formed in the regions between the side walls 30 covered with the silicon nitride film 31 by etching so that the contact holes 41 and 43 may not cause insulation breakdown in the transfer gates 20, it is highly possible that the contact holes 41 and 43 do not reach the silicon wafer 10 and, if etching is performed so that the contact holes 41 and 43 surely reach the silicon wafer 10, it is possible that insulation breakdown is caused in the transfer gates 20 by side etching.
If the conventional semiconductor device fabricating method is applied to fabricating a high-density DRAM having the transfer gates 20 covered with the offset silicon dioxide film 23, the contact holes 43 for connecting the bit lines to the silicon wafer 10, and the contact holes 45 for connecting the bit lines to the transfer gates 20 need to be formed by separate photolithographic processes and etching processes, respectively. Therefore, the conventional semiconductor device fabricating method needs a large number of steps. Since the positions of the contact holes must precisely be determined, the photolithographic process needs a large number of critical layers. Therefore the semiconductor device fabricating method which forms the two sets of contact holes 43 and 45 separately has an increased cost as compared with a semiconductor device fabricating method which forms the two sets of contact holes 43 and 45 simultaneously.